Systolic Architecture of Adaptive Post Detection Integration CFAR Processor in Binomial Distribution Pulse Jamming

A new parallel algorithm for signal processing and a parallel systolic architecture of a CFAR processor with adaptive censoring and post detection integration (API) are presented in the paper. The processor proposed is used for target detection when echoes from targets are performed in conditions of binomial distribution pulse jamming. The property of the algorithm proposed is its ability automatically to determine and censor the unwanted samples corrupted by pulse jamming in both, the two-dimensional reference window and the test cell, before noise level estimation. In case of binomial distribution pulse jamming for big repetition frequency, the censoring capabilities of the algorithm offered from Behar is small and the probability of false alarm is not constant. We offer the vector at the output of the reference window to be sorted and censored again. In such a way the influence of pulse jamming environment over adaptive threshold is reduced to minimum. The systolic architecture of the API CFAR is designed. Computational losses of the systolic architecture are estimated as a number of processor elements and computational steps needed for real-time implementation.